As new military and commercial systems are developed, there is an ever increasing demand for signal sources having unprecedented combinations of output power, efficiency, and transmit bandwidth, with ever decreasing size and weight, as well as extreme linearity requirements. These combined factors have led to an evolution of output signal sources from conventional high power amplifiers to high Power Digital to Analog Converters (PDACs). For instance, communication and navigation systems may demand Radio Frequency (RF), micro- and millimeter-wave Power Amplifiers (PAs), which are similar in operation to high performance Digital-to-Analog Converters (DACs), and which are capable of producing high power over wide frequency ranges with high DC-to-RF efficiency, linear amplitude control over several decades, and with minimum size and/or weight. Many of these systems must also generate linear waveforms with tight spectral control and supply complete digital control of PA and DAC functions for software controlled applications. Currently employed linearization techniques like predistortion, feed-forward, and envelope restoration are limited in bandwidth, temperature range, and efficiency.
Achieving high powers has required DAC designers to use high speed devices, such as Bipolar Transistors, High Electron Mobility Transistors (HEMTs), Insulated Gate Bipolar Transistors (IGBTs), or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in large sizes (i.e., in terms of total gate width or emitter area) to obtain the specified power levels. However, as the high speed device's size increases, a limit may be reached in how large a device can be electrically, how low its terminal impedances can be, and the ability of matching circuits to reach the extremely low impedances on the input and output of the device. Thus, matching to large devices may require large transformation ratios, which are inherently frequency band limited.
Generally, the primary function of a DAC is to convert a low power digital signal to an equivalent analog signal in a fast, efficient, and precise manner. Different architectures may be utilized to create high-speed, low-distortion DACs. DAC circuit topologies include pulse width modulator, oversampling (delta-sigma), R-2R, binary-weighted resistor, and current-scaled DACs. In a pulse width modulator DAC, for example, a stable current or voltage is switched into a low-pass analog filter. The oversampling technique allows for the use of a lower resolution, typically 1-bit, DAC internally. R-2R DACs have variable source impedance depending upon which resistor ladders are switched into the circuit. Weighted resistor DACs have binary weighted resistors which directly scale the analog output voltage. In both topologies, the output voltage is less than the input voltage.
Many high speed DACs utilize some form of non-saturating current-mode switching. A straight binary DAC with one current switch per bit produces code-dependent glitches and may not be an optimum architecture. A DAC with one current source per code level can be shown not to have code-dependent glitches, but may not be practical to implement for high resolutions. Current-scaled DACs scale binary weighted constant current sources or sinks based on the digital input. All of these examples are implemented on a low power level, where the main concern is the conversion of the signal. If a high-power analog signal is needed, another amplifier stage must be cascaded to provide the needed voltage or current drive. Also most of these examples have either pull up or pull down semiconductor devices, not both, so either the rise or fall time for a voltage transition may be very slow.
Thus, it would be desirable to provide a power amplifier with digital to analog conversion features that yields linear or pseudo-linear operation, while maintaining system efficiency.